A conventional active matrix (AM) is shown in FIG. 1. It comprises a matrix of crossing rows and columns of liquid crystal (LC) pixels P1, P2, . . . , Pn. At each cross-point of those rows and columns, switching transistors T1, T2, . . . , Tn are provided. Every pixel P1, P2, . . . , Pn also comprises two capacitors: a storage capacitor C11, C21, . . . , Cn1 which keeps the voltage across the LC constant between two refresh moments, and an intrinsic (parasitic) pixel capacitance C12, C22, . . . , Cn2, formed by the liquid crystal stack (pixel electrode—LC—counter-electrode) itself. When the switching transistors Ti of one row are closed (=made conductive), the respective column voltages are stored on the respective storage capacitors Ci1 of the pixels Pi of that row.
Liquid Crystal on Silicon (LCOS) is a special type of reflective active matrix (AM) liquid crystal displays (LCD), wherein the AM is implemented in a standard silicon process.
A cross-section of a LCOS 1 is shown in FIG. 2. It comprises a semiconductor substrate 2, such as a silicon substrate, with integrated CMOS transistors, and comprises different layers such as a first metal layer 3, a second metal layer 4 and a third metal layer 5 (generally at least four metal layers are provided). On top of the CMOS chip, an LC layer 6 is provided between two alignment layers 7, 8. Thereupon, a glass substrate 9 is provided with an Indium Tin Oxide (ITO) counter-electrode 10, ITO being a conductive and transparent material.
The LC does not operate correctly with a DC voltage, i.e. the pixel voltage has to change in time, the mean value of the pixel voltage (in time) being zero. The electro-optical response of a LC pixel is given in FIG. 3, in a graph in function of the RMS (root-mean-square) voltage. It can be seen that a certain threshold voltage Vth needs to be applied before the LC starts transmitting or reflecting light (depending on the kind of LC).
From the electro-optical response of the LC it can be seen that only a limited part of the curve is suitable for practical implementation. This part is called the “modulation area”, and it is located between a threshold voltage Vth and an inversion voltage Vinv. In Vertically Aligned Nematic (VAN) LC types, the threshold voltage Vth is typically about 2 V, and the modulation voltage Vm is typically about 1 V. With a constant counter-electrode voltage, the pixel electrode must go over a voltage span of 2*(2 V+1 V)=6 V. These voltage values can be quite different for other types of LC.
However, as LCOS is basically a CMOS technology complemented with LC technology, the advantages of CMOS also hold for LCOS. In particular, costs decrease for larger wafers and smaller dimensions of devices on the wafers. At present, in CMOS 0.35 μm processes are used on 8 inch wafers. The maximum gate voltage for transistor devices made in this CMOS process is 3.3 to 3.5 V. This does not seem to be compatible with the voltages required to control the LC.
This problem can be solved by switching the counter-electrode voltage, also called voltage modulation of the common electrode, as described in U.S. Pat. No. 5,920,298.
In an article of S. C. Tan and X. W. Sun, “P-1: Generic design of Silicon Backplane for LCOS Microdisplays”, SID 02 Digest, pp. 200-203, the use of voltage modulation of the common electrode in an LCOS display is described. The voltage on the common electrode is switched between 0 V and the voltage VDD between the two supply rails, in the positive and negative frames respectively. Positive potential across the LC cell is obtained when the voltage applied is referred to the 0 V common cathode, while negative potential is obtained when the voltage on the common electrode is switched to VDD and the applied voltage is less than VDD. This method allows a supply of the same voltage as the LC operating voltage to be used and thus is a low power implementation.
A refresh pixel circuit based on the counter-electrode switching is also described by Tan et al. in the same document. Pixel data from a data line is transferred via a switch or access transistor towards an intermediate storage capacitor, which holds the image data. An in-pixel buffer serves to replicate the voltage stored on the intermediate storage capacitor on a final storage capacitor, from which the pixel data is put on the pixel electrode. The in-pixel buffer presented in the document is either a PMOS source follower or an NMOS source follower. In both cases there is at least a threshold voltage loss over the in-pixel circuitry transistors. This loss decreases the maximum remaining voltage. Moreover, a source follower requires a current source. The current generated by this current source has to be exactly equal all over the chip for each pixel. Another problem is the total power consumption, as the pixel count is typically more than 1 million pixels. This can be solved by pulsed current sources, which in turn require more transistors for each pixel and thus more space on the chip.